SNUG San Jose 2006
Trip Report

The sixeenth annual SNUG San Jose convened March 20-22 at the Santa Clara Marriott hotel in Santa Clara, CA. Attendance was at a record high of 1,294 users! We were filled to capacity and everyone showed great patience throughout the three days of 43 user presentations, 12 panels and 30 tutorials.

SNUG opened on Monday with an official welcome by the Technical Chair, Leah Clark of Broadcom. Addressing a standing-room only crowd, Synopsys CEO and Chairman of the Board, Aart de Geus gave the keynote, providing an overview of the EDA industry today and Synopsys' corporate direction.

Of the many technical sessions for users to take in, there were three new tracks at SNUG. The Manager Track was formulated to attract directors and vice presidents of engineering with program management responsibilities that require an ongoing consideration for both business and technology issues. Also offered were user papers and tutorials on Design for Manufacturing (DFM) and IP, making SNUG a complete forum for engineers in which topics from concept to silicon are discussed.

A highlight for many attendees was guest speaker Steve Wozniak, Apple co-founder and philanthropist, who addressed a packed room with an engaging walk through his experiences as an engineer.

After a full day of technical sessions, attendees got a chance to relax and mingle during two evening events. Day 1 concluded with Synopsys R&D Night, where attendees had a chance to talk shop with Synopsys R&D engineers while enjoying food, beverages and a chance to win prizes. Synopsys executives and product representatives were also on hand to discuss current and up and coming technology. The Interoperability Fair capped off day 2, where attendees had access to over 30 EDA companies who are working with Synopsys to help drive industry solutions to solve electronic design challenges.

With so many users contributing many hours to prepare technical papers and presentations, we're proud to recognize some of our top achievers who won awards at SNUG:

First Place, Best Paper Getting DDRs 'write' – the 1x Output Circuit Revisited Paul Zimmer - Zimmer Design Services * award based on attendee voting
First Place, Best Paper Critical Paths Verification and Debugging with PrimeTime Advanced Features Wei-Si Jiang, National Semiconductor * award based on attendee voting
Second Place, Best Paper SystemVerilog Assertions are for Design Engineers Too! Stuart Sutherland - Sutherland HDL, Inc. and Don Mills - LCDM Engineering * award based on attendee voting
Third Place, Best Paper Physical Layer Verification for PCI Express Dan Steinberg – Integrated Device Technology * award based on attendee voting
Best First-Time Presenter Using SystemVerilog Testbench for High Level Behavioral Modeling of a SIMD Processor Design Shankar Govindaraju, Jayanto Minocha, Kevin Rich, David Dobrikin - Transmeta Corp. * award based on attendee voting
Technical Committee Award (no photo available) VMMing a SystemVerilog Testbench by Example Ben Cohen, VhdlCohen Publishing Srinivasan Venkataramanan, Ajeetha Kumari, Independent * award based on technical committee voting
Technical Committee - Honorable Mention (no photo available) PSL |=> SVA: A Case Study in The Use of Assertions, and The Power of SVA Al Czamara, LOA Technology * award based on technical committee voting
Technical Committee - Honorable Mention (no photo available) Squeezing Test Pattern and Pin Counts using DBIST on a 1.5M Gate Device for a Low Cost Test Solution Pradeep Atur - Cypress Semiconductor Paul Micheletti - Synopsys, Inc. * award based on technical committee voting