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SNUG San Jose 2005
Trip Report
“Mixed-Signal Design and Verification, Static or Dynamic?”
Johnie Au, Cypress Semiconductor
* award based on attendee voting
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“Physical Datapath: Regularized Datapath Placement and Optimization Technology”
Anthony Hill (pictured), Duc Bui and Todd Kroeger, Texas Instruments (co-authored by Anand Arunachalam (pictured), Synopsys, Inc.)
* award based on attendee voting |
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“Fight the Power: Power Reduction Ideas for ASIC Designers and Tool Providers”
Serag GadelRab (pictured), David Bond and David Reynolds, Tundra Semiconductor
* award based on attendee voting |
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“Effects of Specialized Clock Routing on Clock Tree Timing, Signal Integrity and Routing Congestion”
Jesse Craig (pictured), IBM (co-authored by Denise Powell, Synopsys, Inc.)
* award based on attendee voting |
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“Working with PLLs in PrimeTime: Avoiding the 'Phase Locked Oops'”
Paul Zimmer, Zimmer Design Services
* award based on technical committee voting |
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“Fight the Power: Power Reduction Ideas for ASIC Designers and Tool Providers”
Serag GadelRab (pictured), David Bond and David Reynolds, Tundra Semiconductor
* award based on technical committee voting |
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“Using VeraR in the Lab”
K.C. Buckenmaier (pictured), Jie Ding and Changyong Yang, Hifn (co-authored by Chris Spear, Synopsys, Inc.)
* award based on technical committee voting |
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