Technical Session (1:30 PM - 3:30 PM)

• MB1 - User Session - Easing Physical Design Challenges during Synthesis and Power Analysis

  User Paper - DC Graphical, The Promise and the Reality Routing congestion could mean designs fail to reach their performance potential. It may also cause design iterations as it is not detected until after placement. Designers must then change their RTL, or the floorplan, or hope that routing will fix local hotspots. Synopsys's DC Graphical promises to predict and reduce routing congestion during logic synthesis. This paper attempts to validate this claim by analysing the congestion predictions made by DC Graphical to determine its correlation with ICC on several ARM cores. We investigate the sensitivity of DC-Graphical correlation to floorplan information, and test the congestion avoidance features. Philip Watson - ARM Ltd.; Tom Fairbairn – Synopsys, Inc.

  User Paper - A Systematic Analysis of the Correlation between DC-T and ICC This paper presents a systematic analysis of the progression in correlation between DC-T and ICC over multiple versions of both tools. It explores timing correlation in-depth using multiple plots, and highlights interesting observations with reference to the utilization behavior over a range of frequencies. It demonstrates that there are certain choices made by DC-T at specific frequency points that dramatically alter the behavior of ICC - information that can assist design organizations in their decision making process. The results presented in this paper can be valuable for design organizations planning to use DC-T and ICC. Vishwas Rao, J.C. Parker – LSI Corporation; Thomas Wilderotter – Synopsys, Inc.

  User Paper - Hybrid Approach to Power Analysis This paper describes a hybrid approach to perform power analysis using Synopsys Power Compiler that combines ease of RTL simulation with accuracy of gate-level. This paper will cover how this fairly accurate power analysis tool was created, which uses RTL simulation generated saif file and post P&R gate level netlist to generate power reports using Synopsys power compiler. This paper will show how to achieve gate level power accuracy in RTL level simulation time. Using this power analysis methodology, we were able to do power analysis within the accuracy range of +/-5% and with 3.5 times improvement in simulation time. Pankaj Aggarwal, Rashedul Islam - Tensilica Inc.

  
  
  
• MB2 - User Session and Tutorial - Low Power Hierarchical Implementation

  User Paper - A Utility for Leakage Power Recovery within PrimeTime-SI A leakage power recovery utility is presented that runs in the PrimeTime-SI signoff environment to achieve optimal leakage results while preserving the timing performance of the design. This utility analyzes the timing of a design and does cell swapping of high leakage cells to lower leakage cells on paths with positive timing margin. The lower leakage cells are inherently slower, and the utility will determine how many can be used while still achieving the performance target. This utility takes into account crosstalk effects on the timing of the design and supports multiple libraries of different voltage thresholds. It minimizes runtime by reducing the number of timing iterations performed as compared to previous published work in this area. By running in the signoff environment using post layout signoff parasitics and highly accurate timing models it can achieve a much greater leakage recovery over current optimization tools. Bruce Zahn – LSI Corporation

  User Paper - A User's Experience in Developing a Low Power Flow with UPF Historically, implementation and verification of designs utilizing low power techniques such as multi-voltage, power gating and state retention has been a complicated and error prone task using disjointed commanding unique to individual tools and methodologies. The UPF (Unified Power Format) standard from Accellera plans to solve this problem by providing a single set of commands to be used throughout the design flow. The promise of a flexible voltage-aware flow which is portable to new technologies and designs matched ADI's requirements for a low power micro-controller platform. In this paper, we present the development strategy for this proposed low power design. We detail the development of the entire design flow using Synopsys tools along with the power intent described in UPF, from RTL simulation through to layout using MVTOOLS, DC, DFTC, PT-PX, Formality and ICC. We also share best practices and advice on designing for low power as well as the problems encountered and workarounds currently required in the flow. In summary, we provide a user's perspective on moving to the Synopsys UPF flow. Colm O’Doherty, Alan Whooley, Brian Coffey - Analog Devices

  Tutorial - Hierarchical Design Planning in IC Compiler As feature sizes continue to shrink and design complexity continues to increase, many design teams are turning to a hierarchical methodology. This tutorial will showcase the hierarchical design capabilities in IC Compiler to produce designs in minimum area while addressing design closure problems early in the design cycle. This tutorial will focus on design planning and partitioning, hierarchical timing modeling, top level chip assembly, and ICC's Minchip technology. Target audience – All design managers and physical designers Steve Oetting – Synopsys, Inc.

  
  
  
• MB3 - User Session - Advanced Verification Special Topics

  User Paper - Verifying a Challenging Processor Core Using Magellan This paper discusses the work we did with Magellan as hybrid-formal tool for verification of our complex processor core which resulted in finding of 25 design bugs which otherwise might have escaped unnoticed. The paper starts with introduction of formal technology in general and Magellan's hybrid-formal technology in particular and the importance of this technology in our Verification flow. Then, we discuss the criterion for identification of Design blocks suitable for formal verification, steps taken to make the chosen block formal-friendly , various approaches taken in writing input constraints and properties for the block and the impact of these various approaches on effectiveness of verification. In addition, this paper describe various steps taken to ensure faster property convergence since some of the properties are very difficult to prove or falsify. Also, our metrics for formal-closure is discussed. Other interesting applications of formal methods is discussed like its use as a sequential equivalence tool. Various results of running the tool on various blocks are described. We conclude the paper with our findings for the tool and recommendations for people trying to follow a similar approach. Tushar Ringe - Analog Devices

  User Paper - Constraint Solver Diagnostics This paper explores how constraints can be visualized and briefly describes the constraint-solver diagnostic capability recently added to VCS. A large chip-randomization problem is used to illustrate how the diagnostic tool identifies portions of the constraint problem causing performance problems. We then take an in-depth look at a generic split-bus-transaction generator, and analyze the performance of the constraints. From the constraint profile, we identify several possible improvements, and discuss the tradeoff for each approach. Results from each of the modifications are detailed along with a recommendation for this specific constraint problem. Henrik Scheuer – Advanced Micro Devices, Inc.; Alex Wakefield – Synopsys, Inc.

  User Paper - Reducing Failing Testcase Length: Mixing Brute-Force and Intelligence to Extract Meaningful Information from Many Simulations Randomized testcase generation has revolutionized design verification and reduced the effort required to generate long and complex testcases.  These testcases are often as confusing to the human debugger as they are to the DUT.  This paper describes a technique for removing transactions from a failing testcase to produce a much shorter testcase exhibiting the same failure mode.  This technique has been used successfully to reduce transaction sequences verifying a cache memory, and to reduce testcases written in DSP-assembly.  Differences between these two testbenches demonstrate the obstacles which must be overcome in scaling this verification tool. Jonathan Wolfe - Mediatek Wireless, Inc.

  
  
  
• MB4 - User Session and Tutorial – AMS

  User Paper - HSIMplus CircuitCheck on Mixed-Signal Power-Management Designs: A Life-Saver In the same way as DRC tools check the DRM, Hsim CircuitCheck performs rule-based electrical verifications. The following issues have caused silicon failures on our mixed-signal power-management chips: floating gates, high voltage on single oxide transistors, levelshifter insertion and substrate diode biasing. Hsim CircuitCheck addresses each of these issues. We have analyzed the past failures and ascertained that Hsim finds their cause. Consequently, we have used the tool before each tape-out and thus avoided silicon re-spins. A flow has been defined to ensure a timely deployment of the solution in every project. The flexibility of the tool has allowed us to fit it in our top-bottom methodology and check the circuits all along their design phase. Vincent Bligny - STMicroelectronics

  User Paper - W-element and S-parameter Models for High Speed Board traces - Do We Need Both? Timing and Signal Integrity analysis of high speed serial interfaces such as PCIE and XAUI require frequency dependent transmission line models for modeling the physical losses in package and board traces. In HSPICE the first option is to use W-element models with different level of complexity (RLGC, TABLE Models). In addition we convert the W-element models of differential pair XAUI compliance traces into 4 port S-parameter models. By comparing the first and second resonance frequency of the insertion loss between VNA measurements and HSPICE S-parameters, we are able to identify important differences between the RLGC and TABLE models. Johann Nittmann, Scott Meninger - Cavium Networks

  Tutorial - Fast and Accurate Eye Data Generation with HSPICE This tutorial will introduce the new statistical eye generation feature available in HSPICE 2008.09. Analysis of high-speed serial interfaces requires processing of millions of bits of data making analysis by traditional analysis tools computationally expensive. Eye diagrams are used extensively in the evaluation of high-speed serial interfaces and as a fundamental performance metric for high-speed serial interfaces in the bit error rate (BER). Statistical eye diagram techniques allow eye diagrams and BER to be generated quickly and accurately. Target audience: Board-level signal integrity engineers, particularly those working with high-speed serial protocols. Tetsuhisa Mido - Synopsys, Inc.

  
  

Technical Session (3:45 PM - 5:15 PM)

• MC1 - Tutorial - Removing Congestion with Design Complier
  

  With its accurate prediction of post layout results during synthesis, Design Compiler Topographical technology has established itself as the solution for fastest turn-around-time (TAT). Can topographical help reduce congestion to improve TAT further? What are the latest advancements with the topographical technology? Join this session to learn the answers and hear directly from Synopsys R&D experts how topographical can not only help you predict congestion during synthesis but can also optimize the design for easing congestion. Hear from your peers about their experience with this breakthrough technology. A moderated Q&A session follows the discussion . Target audience: Designers responsible for RTL Coding/Synthesis, physical implementation and/or the implementation flows. Also, Project Managers looking to minimize the effects of ever shrinking schedules. Phil Watson – ARM Ltd. Jeff Winkler – Synopsys, Inc. Janet Olson – Synopsys, Inc.




• MC2 - Vision Session - Coping with Variability
  

  As we progress into the sub-90nm technology, variability in design performance becomes an increasing concern. In this presentation, we will discuss the impact of variability and conundrum it poses with design margins. The talk will show some of the visible signs of variability in the industry. The presentation will then focus on exploring causes for variability and outlining some of the approaches to deal with variability during design. Finally, we will touch upon changes in the technology that could eliminate variability or reduce its impact for a few generations of silicon technology. Target audience: All physical designers and design managers. Narendra Shenoy – Synopsys, Inc.

  
  
  
• MC3 - User Session - SystemVerilog Tips and Techniques

  User Paper - Just When You Thought It Was Safe to Start Coding Again... Return of the SystemVerilog Gotchas All programming languages have gotchas: easy-to-make errors or misunderstandings that look OK but don't work, don't behave as expected, or differ between tools. Knowing about SystemVerilog's gotchas helps prevent making these mistakes, and eases detecting and debugging them when they do occur. Sutherland and Mills published a book of gotchas last year, but there are many more. This paper presents a selection of additional gotchas that have bitten the author and his colleagues over the years, some of them very nasty. Shalom Bresticker – Intel Corp.

  User Paper - Clock Domain Crossing (CDC) Design & Verification Techniques Using SystemVerilog Important design considerations require that multi-clock designs be carefully constructed at Clock Domain Crossing (CDC) boundaries. This paper details some of the latest strategies and best known methods to address passing of one and multiple signals across a CDC boundary. Included in the paper are techniques related to CDC verification and an interesting 2-deep FIFO design for passing multiple control signals between clock domains. Although the design methods described in the paper can be generally implemented using any HDL, the examples are shown using interesting SystemVerilog techniques. Clifford Cummings - Sunburst Design, Inc.

  
  
  

• MC4 - User Session - User Experiences with XA
  

  User Paper - XA Technology Integration in Custom Power MOSFET Analysis Flow The use of discrete power MOSFET devices has increased in several fields of application thanks to their good performances in terms of fast switching characteristics and lowest RDS(ON). Internal and external electrical characteristics of a power MOSFET by STMicroelectronics have been investigated using a distributed model. A new CAD tool has been developed to extract layout parasitics and the SPICE-like netlist to be simulated with different operating conditions. Overcoming the standard SPICE simulators approach, this article shows how the new XA Synopsys Technology Fast SPICE approach has been adopted by STMicroelectronics. Usage of XA fast SPICE simulator has demonstrated an advantage in terms of capacity and speed with negligible loss of accuracy with respect to standard golden SPICE simulator. Giuseppe Greco - STMicroelectronics; Claudio Rallo - Synopsys, Inc.

  User Paper - Acceleration of Analog Simulations with Synopsys XA For modern sub-micron process, the complexity of circuitry and models makes simulation time a critical issue for a designer. This is especially true in case of high-sensitivity analog circuits, where sacrificing accuracy for speed is not an option. Post-layout simulations are the most time-consuming, since taking into consideration DFM effects and detailed parasitic extraction leads to vast netlist. For more than a year our team was looking for fast and accurate analog simulator for our specialized I/O interfaces and full-custom analog IP. We wanted the tool to integrate easily into our existing design flow, which is based on a well-known and widely used in the industry Spice-like simulator. We evaluated 6 tools, and have positive impression from a new Synopsys product: XA. For pre-layout simulations it demonstrates excellent speed-accuracy tradeoff and reliable behavior. It has issues with post-layout simulations, but for many of them we could accelerate runtime also. Depending on testcase, we achieved from 3 to more than 100 times acceleration, with a good match to reference results. The testbenches include a range of common analog blocks: PLL, DLL, high-speed transmitter/receiver, a DCDC converter. The paper describes evaluation methodology and results, detected issues, strong and weak qualities of XA simulator, as well as desired features for further improvement Nitchougovskaia Larissa - AMD

Technical Session (9:00 AM - 11:00 AM)

• TA1 - User Session - Test in Modern World
  

  User Paper - User Experience with Small Delay Defect ATPG Having accepted the fact that we needed to augment our test methodology to include better quality at speed tests, we attempted to perform Small Delay Defect (SDD) ATPG as prescribed in the Synopsys documentation. Much to our surprise we found that 60% of the faults had negative slack. Obviously we had a problem with our slack data. This paper describes the steps taken to ensure good quality slack data that result in good quality Small Delay Defect Test Patterns. We describe how to constrain Primetime to minimize the number of paths with negative slack, and how to use the SDC's written from Primetime to constrain TetraMax for SDD ATPG. Finally, we substantiate our methodology with test results from a manufacturing run. Zahi Abuhamdeh, Vincent D’Alessandro - TranSwitch Corporation; Mona Marmash – Synopsys, Inc.

  User Paper - Case Study - Physical Impact of Scan and Compression Scan has historically been a low priority concern for the physical designer. Generally consisting of less than 50 scan chains, basic optimization algorithms effectively optimize scan wire length. Scan chain end points to external pins or ports have also been a low priority since they number less than a hundred or so in designs that have hundreds of thousands on nets. Virtually all modern design now includes scan compression. The effect on the scan architecture is to effectively create hundreds, sometimes more than a thousand scan segments in the physical design. These segments are then consolidated through a DFT compressor structure to a relative few external pins or ports. This Case Study will consider the physical impact of large numbers of scan segments and compression logic on the design. We investigate scan optimization algorithms and strategies using available wire length, congestion, and timing metrics. Ralph Jankowich - Qualcomm; Howard Gainey, Brad MacMonagle – Synopsys, Inc.

  User Paper - TetraMAX ATPG Power-Aware Results on the ARM Cortex-A8 Microprocessor Power consumption during scan test is continuing to be a growing area of concern.  This paper examines some recent functionality in TetraMAX ATPG that makes use of existing on-chip low power infrastructure to reduce the peak power requirements during at-speed test.  In particular, the TetraMAX ATPG engine utilizes clock-gating cells to lower switching activity during test.  We will show that using this capability allows the DFT engineer to manage at-speed switching activity to within the limits of the design.  We will also outline techniques for verifying these lower power patterns in PrimeTime PX. Frank Frederick, Teresa L. McLaurin- ARM, Inc.

  
  
  
• TA2 - User Session and Tutorial - Physical Design Experiences
  

  User Paper - Accurate Timing Closure with Voltage Aware STA In the RTL2GDSII implementation flow for SoC designs in nanometer process technologies, analyzing the Signal integrity (SI) and dynamic voltage drop (DvD) effects is critical. There is an increased risk of timing and functional failures of the design due to the effects of DvD and SI. The DvD causes change in the supply voltage at each instance. Since this voltage variation is not accounted for, in the normal Static Timing Analysis (STA) and SI flows and the results can be inaccurate. It can result in setup and hold time failures that the STA and SI analysis flow may not flag or in a glitch noise failure that is not flagged by the SI analysis flow. Traditional methodologies using a fixed budget for IR drop and timing margins are inadequate. This paper presents a new methodology to incorporate the voltage variation due to DvD within our timing and SI analysis flows. This Voltage-aware STA enables a more accurate timing closure for designs and hence increases the chance of having first pass yield Silicon. Anil Gundurao, Ali Eltoukhy – Cypress Semiconductor

  User Paper - Unintentional Forward Biased Diode Checker Detecting unintentional Forward Biased Diodes(FBDs) created as a result of improperly placed gate / antenna tie downs, power up sequence issues and improperly biased wells, is an important part of any DRC, LVS, ERC checking methodology to guarantee a first time right, quality design. Unintentional Forward Biased Diodes have always been part of IC design but the introduction of isolated PWells and the need to power down sections of the chip for low power applications, potential for creating FBDs has dramatically increased. This paper will show examples of how FBDs are created and a method used to detect them. Arnold Baizley, Joe Iadanza– IBM Corporation

  Tutorial - IC Compiler 2008.09 Layout Editing Demo This demo will include a tour of the overall interface for those who haven’t used Layout Editing in ICC yet, the Advanced Route Tool for DRC-aware single and multi-net interactive routing, and the Error Browser for managing error correction activities. Target audience: All physical designers using IC Compiler. Dan Guilin, John Griner – Synopsys, Inc.

  
  
  
• TA3 - User Session - VMM in Action
  

  User Paper - Verifying Designs for Wireless-Broadband Applications Using SystemVerilog and Next Generation VMM Verifying Designs for Wireless-Broadband Applications Using SystemVerilog and Next Generation VMM This paper describes how SystemVerilog and Verification Methodology Manual (VMM) were effectively used to verify a complex wireless application that was based on the IEEE 802.16 standard. The verification effort was successful in catching a large number of bugs, and achieving verification closure by the use of functional coverage and self-checking testbench architecture. The Design Under Test (DUT) in this case was also complex, and verifying it was challenging. This paper attempts to describe how an informed use of VMM and its next-generation application -- Register Abstraction Layer (RAL), object-oriented concepts, and SystemVerilog features such as constrained randomization and Direct Programming Interface (DPI) helped overcome these challenges. Heedo Jung - Samsung Electronics Co.; Aditya Kher – Synopsys, Inc.

  User Paper - Applying VMM to the Verification of an Industrial Controller Design This paper details some mechanisms used in the verification of a highly scalable multi-FPGA industrial controller. It describes how VMM made it easier to execute the dynamic checks in a random environment as well as in directed test cases. Analyzing specific examples, the paper also demonstrates the power of callbacks when used for checking and propagating values to various points in the system. The paper concludes by reporting problems encountered and lessons learned during this verification project. Iman Abdo, Ryan Yuan Chen - Patni Computer

  User Paper - Dealing with Inexactitude in VMM Verification Verification is often designed around knowing precisely what is going on, such as how data will be transformed, where data will be sent to, and the precise state of the DUT. However, situations often arise where this information is not easily determined, normally due to the exact DUT state not being known. This paper deals with methods to enhance VMM data classes and transactors to deal with these situations, looking at typical cases to show techniques:       * A generic case in which multiple simultaneous events are handled       * Determining the "closest match" when a mismatch happens to aid debugging       * Dealing with interrupts which are read on the fly       * Dealing with unknown packet routing in a switch-type application during learning phase (ie: don't know which port item will go to)       * Dealing with unknown packet transformations of portions of a packet in scoreboarding (ie: don't know what full packet will look like) Joseph Manzella – LSI Corporation

  
  

• TA4 - Tutorial - Technical Insight into SoC Prototyping Using FPGAs
  

  This tutorial is presented in three parts: 1) Manipulation of ASIC Design for Implementation in FPGA The third law of prototyping is that ASIC designs are FPGA-Hostile. This session will give guidance on the manipulation that can be performed on an ASIC design in order to map it efficiently into FPGA. We show how to handle ASIC cells instantiations, full ASIC netlists, IP without RTL available, Designware IP, Memory instantiations, clock gating and partitioning across multiple FPGAs. These are all possible without alterations to the RTL itself.  2) An application overview of a real-life prototyping project using HAPS hardware at Silicon Optix, Toronto, Canada.  3) Tips and Tricks for on-board RTL Debug using TotalRecall Technology We show how RTL-level visibility is maintained even when the ASIC design is running in FPGA. VCS simulator is linked to the Identify Pro debugger, employing TotalRecall technology. We show a live demo of a small example design running on Synopsys’s High-Performance ASIC Prototyping System, using OVL Assertions to trigger the capture of self-contained test-cases for later replay and analysis in a normal VCS simulator. Target audience: Emulator users and other engineers requiring much faster verification throughput and an ability to provide platforms for internal and external software application development. Pete Calabrese, Doug Amos – Synopsys, Inc.

  
  
  

  Technical Session (12:45 PM - 2:15 PM)
  

• TB1 - Tutorial - Achieving Ultra-High Test Quality: Timing- and Power-Aware ATPG: Part I
  

  TetraMAX ATPG now provides timing- and power-aware patterns that can significantly improve the quality of your manufacturing tests compared with standard ATPG technologies. This technical overview will describe in detail how you can use new TetraMAX ATPG features to achieve a step-increase in test quality without impacting your DFT flow. In addition, Galaxy Test product updates will be covered, including new hierarchical flow features for power savings and DFT MAX adaptive scan compression enhancements to lower test costs. Part I:     • Small Delay Defect ATPG (30 min)     • Power-Aware ATPG (30 min)     • 2007.12 Updates (30 min)         - TetraMAX ATPG reads SDCs         - DFT MAX compression architectural flexibility         - SCANDEF usage in Galaxy Test updates Target audience: Implementation and DFT engineers, as well as managers, interested in realizing ultra-high test quality Adam Cron – Synopsys, Inc.

  
  
  
• TB2 - Tutorial - Physical Design Update

  This update tutorial presents the latest features and methodologies of IC Compiler. The main topics covered in this session include improvements in runtime and quality of results along with new features for low-power design, improvements in timing/SI closure, MCMM, and DFM/Routing areas. The second half of this session will go deep on selected CTS Topics. Target audience: All physical designers and design managers. Dave Power – Synopsys, Inc.

  
  
  
• TB3 - Tutorial - Constraint Diagnostics and Guidelines
  

  This tutorial explores how constraints can be visualized, and how the solver approaches the mathematically difficult problem of finding a valid solution. The two solver modes are discussed, with the different approaches the solver uses for each. An overview of the constraint-solver diagnostic capability will be provided. Some sample diagnostic messages and how the constraints can be recoded will be discussed. Finally, some general constraint guidelines, and how to efficiently code constraints will be presented. Target audience: Verification engineers familiar with SystemVerilog testbench and the constraint language who are looking to add constraints to their testbench or improve their use of constraints.

  
  
  
• TB4 - Tutorial - Improving Design Efficiency from Concept to Final FPGA Implementation with ESL Design and Physical Synthesis

  As FPGA geometries shrink, synthesis and place-and-route implementations increase.  Traditional wire load model synthesis pushes timing closure problems to the end of the design cycle, resulting in multiple iterations.  This session demonstrates methods for achieving faster timing closure by combining ESL design with physical synthesis. Technology session topics: Part I:   ESL design – Using Simulink/MATLB to develop high level vendor independent RTL code Part II:  Faster turn-around time using Physical Synthesis to implement an RTL to placed gates flow. Target audience – Design managers, DSP Algorithm developers, and FPGA designers Sara Steigerwald – Synopsys, Inc.

  
  
  

  Technical Session (2:30 PM - 4:00 PM)
  

• TC1 - Vision Session and Tutorial – The Limits of Compression and Achieving Ultra-High Test Quality: Part II
  

  Vision Session - The Limits of Compression Synopsys Fellow Dr. Thomas W. Williams will present his unique vision into test compression technology and its future possibilities. The use of scan-based compression techniques is becoming mandatory on current designs. Small delay fault testing is one of the fault targets which is causing an expansion in the test data volume. While high compression is desired to hold the test costs within limits, it is important to understand what bounds exist that govern the ultimate compression. Dr Williams’ position is simply that the network on chip determines the maximum compression not the engineer or for that matter not the Test EDA salesperson. Dr. Thomas W. Williams – Synopsys, Inc.

  Tutorial - Achieving Ultra-High Test Quality: Timing and Power-Aware ATPG: Part II TetraMAX® ATPG now provides timing- and power-aware patterns that can significantly improve the quality of your manufacturing tests compared with standard ATPG technologies. This technical overview will describe in detail how you can use new TetraMAX ATPG features to achieve a step-increase in test quality without impacting your DFT flow. In addition, Galaxy Test product updates will be covered, including new hierarchical flow features for power savings and DFT MAX adaptive scan compression enhancements to lower test costs. Part II:     • 2008.09 Updates         - DFT MAX compression features         - TetraMAX ATPG features   Target audience: Implementation and DFT engineers, as well as managers, interested in realizing ultra-high test quality Adam Cron – Synopsys, Inc.

  
  
  
• TC2 - Tutorial - Getting the Best Performance out of PrimeTime

  This tutorial highlights best practices to get the most out of your PrimeTime runs. It will cover the newest features in 2008.6 release and identify opportunities to tune scripts to take advantage of the latest improvements to PrimeTime. Specific strategies covering both PT and PTSI, including use of PrimeTime’s Distributed Multi-Scenario Analysis feature (DMSA), will be presented and results shared for the 2008.6 release. Target audience: This tutorial is for all new and existing users responsible for analysis and signoff scripts in PrimeTime.

  
  
  
• TC3 - Tutorial - Creating Reusable Testbenches Using Scoreboards and Partitioned Environments
  

  Modern testbench methodologies emphasize a hierarchical, modular approach to testbench design. Envisioning how to create generators, drivers and monitors is normally a straight forward process since these building blocks mirror the functional building blocks of the design. However, adding the scoreboard, self checking and environment portions of the testbench is often more difficult. Without carefully planning a strategy for these key testbench components you can easily end up with testbench building blocks that are difficult to reuse. This presentation covers the planning, organization and components necessary to create a reusable testbench environment. Finally it will discuss the new VMM Scoreboard and Environment Composition classes which help make the implementation easier. Target audience: Verification engineers familiar with SystemVerilog testbench and layered testbench methodologies.

  
  
  
• TC4 - Panel - Modern Optimization and Verification Strategies for Complex FPGA Designs
  

  Modern design and verification environments, using the SystemVerilog language and methodologies, can make FPGA designers more efficient, resulting in reduced debug time in the lab, and creating a higher quality product in less time.   Join this panel to hear from your peers about how these methodologies were implemented and how it helped with creating higher quality product in less time.  Target Audience: This is an informative panel for FPGA Design managers, and FPGA Design/Verification engineers.