SNUG Singapore 2008
August 6, 2008
Call for Papers

The Call for Papers EXTENDED!

Submitting a paper to SNUG Singapore 2008 is an excellent way to increase the visibility of your successful projects both in your own company and within the South Asia IC design community. If you have information on high-level or physical design methodology, RTL-to-GDSII design flows, system simulation, mixed-signal design, design for manufacturing or experiences with Synopsys tools that would be of interest to other users, we'd like to hear from you.

Never done it before? It's easy. To submit an abstract, specify in a few paragraphs the idea for your SNUG Singapore paper. Send your submission via email to snugsingapore@synopsys.com. The deadline to submit an abstract is 9 May, 2008.

For the complete author submission timeline, please view the Author's Kit. If you have any questions, please contact the SNUG Signapore Team .

Preliminary topics include (but are not limited to):

Physical Design :
- Scripts and Makefiles
- Physical Synthesis
- Place and Route
- Timing Closure
- Floorplanning
- Clock Tree Synthesis
- Timing Budgeting
- Design for Reliability
- Signal Integrity
- Power Planning
- Physical Verification
- RC Extraction
- Low Power Design
- Hierarchical Design
- Design For Yield (DFY)

Design for Manufacturing :
- Technology CAD (TCAD)
- Optical Proximity Correction (OPC)
- Phase Shift Mask (PSM)
- Mask Data Preparation

Functional Verification:
- Assertion Based
- System Verilog
- Formal Techniques
- Verifying with Embedded IP
- Speeding up Simulation
- Mixed HDL Verification
- Constrained, random verification techniques

Synthesis:
- Scripts and Makefiles
- Design Coding Styles
- Datapath design
- Integrating IP
- Low Power Designs
- Testable Designs

Static Timing Analysis:
- Scripts and Makefiles
- CCS Libraries
- Multi-corners, Multi-mode

Test:
- Design-for-Test
- At Speed Testing
- Scan Compression
- ATPG

Mixed-Signal Design and Verification:
- Custom Layout
- Design Entry
- Functional & Timing Verification
- Low Power Design
- Mixed-Signal Verification
- Verilog-AMS, VHDL-AMS
- Static Timing Analysis
- Device Modeling

If you have any questions, please contact the SNUG Singapore Team.